Differential circuit and receiver with same

ABSTRACT

A differential circuit including a differential amplifier circuit having a differential element provided in a signal input circuit, a constant current source connected to the differential element, and loads respectively connected to the differential element, and a source follower circuit that outputs a differential voltage based on voltage drops developing across the loads, includes a current supply circuit that supplies a given current to the loads connected in series with the differential element when the differential element is off.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention generally relates to differential circuits and receivingdevices having the same used for small-amplitude and current-modehigh-speed serial digital transmission signals, and more particularly,to a differential circuit having an input circuit and a buffer circuitincluded in a receiving device used for receiving high-speed serialdigital transmission signals. The input circuit needs to handle arail-to-rail input common-mode range having a terminal common-modevoltage near the ground level voltage to the power supply voltage and adifferential output buffer circuits having a constant common-modepotential, that is independent of the input common-mode voltage arenecessary for processing the high-speed signals inside the chip.

2. Description of the Related Art

Conventionally, the interface standards for the digital signals such asthe transistor-transistor logic: TTL (2.0/0.8) and the complementarymetal-oxide semiconductor: CMOS (3.3/0.0) have been used in the serialdigital transmission. However, these standards are standardized for thedigital signals that have relatively large voltage amplitudes, and thereis a problem in that signal transmission delay is relatively large.Therefore, it is difficult to realize the high-speed serial digitaltransmission, which is demanded in these years, between the devices withthe use of the above-mentioned standards.

In order to solve the aforementioned problem, small-voltage swing andcurrent-mode differential transmission standards have been proposed inrecent years. An example of the standards is LVDS (low VoltageDifferential Signaling).

The LVDS standard only specifies the use of a differential currentdriver and terminal impedance. Therefore, the input differential circuitthat meets the LVDS standard has to operate at an arbitrary common-modeterminal voltage. According to the standard, a current driver is usedfor a transmitting circuit (hereinafter, referred to as LVDStransmitter) drives a signal that meets the LVDS standard (hereinafter,referred to as LVDS signal) so that 350 mV of amplitude may be availableas a terminal voltage, when the terminal impedance of 100 Ω isconnected. On the other hand, the receiving circuit of the LVDS signal(hereinafter, referred to as LVDS receiver) is configured so that aterminal voltage difference of approximately 350 mV can be received,corresponding to the common-mode terminal voltage of 0 to 2.4 V. That isto say, if the power supply voltage Vcc of 2.5 V is set, the amplifiercircuit in the input circuit of the LVDS receiver is to operate thecommon-mode input signal, which is substantially equal to the powersupply voltage. The rail-to-rail operation denotes the operation of thecommon-mode input signals substantially equal to the power supplyvoltage.

Conventionally, as a structure of a rail-to-rail differential amplifiercircuit with the use of CMOS technology, a topology has been proposed sothat the limits of the both common-mode operation ranges may becompensated by connecting the differential amplifier circuit of anN-channel element in parallel with the differential amplifier circuit ofa P-channel element.

Under the circumstances, the output from the amplifier circuit arrangedas the input circuit is demanded to have desirable signal quality forthe amplifier circuit provided in the later stage. That is, it ispreferable that the differential output from the amplifier circuit ofthe input circuit has a constant common-mode potential to be independentof the input common-mode voltage in order to operate the high-speedsignals inside the chip. Moreover, an appropriate buffer circuit has tobe included to drive the load inside the chip.

For example, U.S. Pat. No. 6,320,422 discloses the technique of feedbacking the output voltage in the buffer circuit to control andstabilize the differential output in the differential amplifier circuit.Hereinafter, the aforementioned patent will be referred to as aconventional technique 1, and will be described with reference to FIG.1.

Referring to FIG. 1, the conventional technique 1 is configured toinclude a differential amplifier circuit having an N-channeldifferential amplifier circuit 801 and a P-channel differentialamplifier circuit 813, a complementary source follower circuit 826 and acomplementary source follower 828. Outputs (806 and 818) from thedifferential amplifier circuit are input into the complementary sourcefollower circuit 826, and in the same manner, outputs (808 and 820) fromthe differential amplifier circuit are input into the complementarysource follower 828. The above-mentioned two complementary sourcefollower circuits 826 and 828 serve as the buffer circuits that drivethe internal loads.

The N-channel differential amplifier circuit 801 includes an N-channeldifferential element 802, active loads 812 and 810, and a constantcurrent source 804. The N-channel differential element 802 has a pair ofN-channel MOS transistors (field-effect transistors are preferable.Hereinafter, simply referred to as transistors). The active loads 812and 810 are the loads of the N-channel differential element 802. Theconstant current source 804 is connected to the N-channel differentialelement 802. In the same manner, the P-channel differential amplifiercircuit 813 includes a P-channel differential element 814, active loads822 and 824, and a constant current source 816. The P-channeldifferential element 814 has a pair of P-channel MOS transistors. Theactive loads 822 and 824 are the loads of the P-channel differentialelement 814. The constant current source 816 is connected to theP-channel differential element 814.

In the above-mentioned configuration, an output node 830 of thecomplementary source follower circuit 826 is connected to the activeloads 810 and 822 respectively, which are composed of the N-channel MOStransistors. That is, the both edges of the voltages of the active loads810 and 822 are controlled to feed back according to the output voltageof the complementary source follower circuit 826. In the same manner, anoutput node 832 of the complementary source follower circuit 828 isconnected to the active loads 812 and 824 respectively, which arecomposed of the N-channel MOS transistors. That is, the both terminalvoltages of the active loads 812 and 824 are controlled to feed backaccording to the output voltage of the complementary source followercircuit 828. This can prevent the operation points of the active loads810, 812, 822, and 824 from shifting from the linear region into thesaturation region. The operation is thus configured to always operate inthe linear region, which prevents a non-linear operation of thedifferential output so as to stabilize the differential outputs.

However, with the configuration as disclosed in the conventionaltechnique 1, it is impossible to stabilize the common-mode potentials ofthe output voltages from the two complementary source follower circuitsprovided in the output circuit, if the input common-mode voltage makesthe two complementary source follower circuits operate in differentmodes. In addition, if the output voltage is configured to feed back asdisclosed in the conventional technique 1, there may arise anoscillation by switching the output voltage at a high speed.

SUMMARY OF THE INVENTION

The present invention has been made under the above-mentionedcircumstances and has an object of providing the differential circuitand the receiving circuit having the same. The differential circuit iscapable of outputting a differential output having a constantcommon-mode potential without a feed back structure, and includes abuffer circuit suitable for driving the load inside the chip.

In order to achieve the above-mentioned objectives, according to oneaspect of the present invention, preferably, there is provided adifferential circuit including a differential amplifier circuit having adifferential element provided in a signal input circuit, a constantcurrent source connected to the differential element, and loadsrespectively connected to the differential element; and a sourcefollower circuit that outputs a differential voltage based on voltagedrops developing across the loads, characterized by further comprising acurrent supply circuit that supplies a given current to the loadsconnected in series with the differential element when the differentialelement is off. It is thus possible to output the differential outputhaving a common-mode potential without a feed back structure and realizethe source follower circuit serving as a buffer circuit suitable fordriving the internal load inside the chip.

According to another aspect of the present invention, preferably, thereis provided a differential circuit including a first differentialamplifier circuit having a first differential element provided in asignal input circuit, a first constant current source connected to thefirst differential element, and a first and a second loads respectivelyconnected to the first differential element; a second differentialamplifier circuit having a second differential element provided in thesignal input circuit, a second constant current source connected to thesecond differential element, and a third and a fourth loads respectivelyconnected to the second differential element; a first source followercircuit that outputs a first differential voltage based on voltage dropsdeveloping across the first and second loads; and a second sourcefollower circuit that outputs a second differential voltage based on thevoltage drops developing across the third and fourth loads,characterized by further comprising a first current supply circuit thatsupplies a given current to the first and second loads when the firstdifferential element is off; and a second current supply circuit thatsupplies the given current to the third and fourth loads when the seconddifferential element is off. It is thus possible to output thedifferential out put having a common-mode potential without a feed backstructure and realize the first and second source follower circuitsserving as buffer circuits suitable for driving the internal load insidethe chip.

According to another aspect of the present invention, preferably, thereis provided a receiving device having a differential circuit including adifferential amplifier circuit having a differential element provided ina signal input circuit, a constant current source connected to thedifferential element, and loads respectively connected to thedifferential element; and a source follower circuit that outputs adifferential voltage based on voltage drops developing across the loads,characterized by further comprising a current supply circuit thatsupplies a given current to the loads connected in series with thedifferential element when the differential element is off. It is thuspossible to output the differential out put having a common-modepotential without a feed back structure and realize the source followercircuit serving as a buffer circuit suitable for driving the internalload inside the chip.

According to another aspect of the present invention, preferably, thereis provided a receiving device having a differential circuit including afirst differential amplifier circuit having a first differential elementprovided in a signal input circuit, a first constant current sourceconnected to the first differential element, and a first and a secondloads respectively connected to the first differential element; a seconddifferential amplifier circuit having a second differential elementprovided in the signal input circuit, a second constant current sourceconnected to the second differential element, and a third and a fourthloads respectively connected to the second differential element; a firstsource follower circuit that outputs a first differential voltage basedon voltage drops developing across the first and second loads; and asecond source follower circuit that outputs a second differentialvoltage based on the voltage drops developing across the third andfourth loads, characterized by further comprising a first current supplycircuit that supplies a given current to the first and second loads whenthe first differential element is off; and a second current supplycircuit that supplies the given current to the third and fourth loadswhen the second differential element is off. It is thus possible tooutput the differential out put having a common-mode potential without afeed back structure and realize the first and second source followercircuits serving as buffer circuits suitable for driving the internalload inside the chip.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the present invention will be described indetail with reference to the following drawings, wherein:

FIG. 1 is a block diagram showing a configuration of a differentialcircuit 800 of a conventional technique 1;

FIG. 2 is a circuit diagram showing the configuration of a differentialcircuit 100 used in the description of the present invention;

FIG. 3 is a view showing an operation of the differential circuit 100shown in FIG. 2;

FIG. 4 is a circuit diagram showing the configuration of a differentialcircuit 200 used in the description of the present invention;

FIG. 5 is a view showing the operation of the differential circuit 200shown in FIG. 4;

FIG. 6 is a graph showing simulation results of the differential circuit200 shown in FIG. 4;

FIG. 7 is a circuit diagram showing the configuration of a differentialcircuit 300;

FIG. 8 is a block diagram showing the configuration of a differentialcircuit 400 to be designed with a topology of the differential circuit300 shown in FIG. 7;

FIG. 9 is a view showing a circuit structure of the differential circuit400 shown in FIG. 8;

FIG. 10 is a graph showing simulation results of the differentialcircuit 400 shown in FIG. 8;

FIG. 11 is a graph showing simulation results of a case where the biaspotentials VBp and VBn are set to ½ of Vcc; and

FIG. 12 is a block diagram showing a receiving device 1000 having thedifferential circuit 400 of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(Principle)

A description will now be given of the principle of the presentinvention, before the description of preferred embodiments of thepresent invention.

The present invention relates to a differential circuit and a receivingdevice having the same. The differential circuit is capable ofoutputting a differential output having a constant common-mode potentialwithout a feed back structure, and includes a buffer circuit suitablefor driving the load inside the chip.

In order to achieve the above-mentioned object, in the differentialcircuit used for processing high-speed serial digital transmissionsignals, a topology having a combination of the source follower circuitsin the structure of the output circuit is added to another topology inwhich the both limits of the common-mode operation range are compensatedby connecting the differential amplifier circuit composed of theN-channel element in parallel with the differential amplifier circuitcomposed of the P-channel element. Thus configured circuit according tothe above-mentioned topologies is capable of retaining a substantialrail-to-rail common-mode range and a high-speed buffering.

However, if the above-mentioned two topologies are simply combined inthe circuit design, there arises a problem in that the common-modepotential of the differential output, which is available at thedifferential amplifier circuit, varies depending on the common-modevoltage in the input circuit. In order to solve the aforementionedproblem, the differential circuit for operating the high-speed serialdigital transmission signals in accordance with the present invention isconfigured so that a certain bias potential may be applied to the nodeof the source follower circuit of the output circuit. This is realizedby, for example, providing a complementary bypass circuit between acurrent source and an input node of the complementary source followercircuit. The current source is connected to the respective common nodesof the differential amplifier circuits respectively composed of theN-channel element and the P-channel element. This bypass circuit servesas a current supply circuit that supplies a given amount of current tothe load, when the differential amplifier circuit is not operating. Itis thus possible to stabilize the operation point of the complimentarysource follower circuit in the output circuit, regardless of thecommon-mode voltage in the input circuit. As a result, it is possible tocompose a buffer circuit in which a differential output having aconstant common-mode voltage is available.

A description will be given in detail, with reference to the drawing.FIG. 2 is a circuit diagram of a differential circuit 100, in which thetopology having a structure of a combination of the source followercircuits in the output circuit is added to another topology in which theboth limits of the common-mode operation range are compensated byconnecting the differential amplifier circuit composed of the N-channelelement in parallel with the differential amplifier circuit composed ofthe P-channel element.

As shown in FIG. 2, the differential circuit 100 is configured toinclude an N-channel differential amplifier circuit 1 (the differentialamplifier circuit composed of the N-channel element) and a P-channeldifferential amplifier circuit 2 (the differential amplifier circuitcomposed of the P-channel element), and two source follower circuits 5and 6.

In this configuration, the N-channel differential amplifier circuit 1includes an N-channel differential element 11, resistance loads 103 and113, and a constant current source 140. The N-channel differentialelement 11 includes two N-channel MOS transistors (field-effecttransistors are preferable. Hereinafter, simply referred to astransistors) 101 and 111. The resistance loads 103 and 113 arerespectively connected to drain nodes of the N-channel MOS transistors101 and 111. The constant power source 140 is commonly connected tosource nodes of the two N-channel MOS transistors 101 and 111. In thesame manner, the P-channel differential amplifier circuit 2 includes aP-channel differential element 12, resistance loads 104 and 114, and aconstant current source 141. The P-channel differential element 12includes two P-channel MOS transistors 102 and 112. The resistance loads104 and 114 are respectively connected to drain nodes of the P-channelMOS transistors 102 and 112. The constant power source 141 is commonlyconnected to source nodes of the two P-channel MOS transistors 102 and112.

The source follower circuit 5 serves as an output circuit that outputs alower voltage of the differential signal, and includes an N-channel MOStransistor 105, a constant current source 151, a P-channel MOStransistor 106, and a constant current source 161. A gate node of theN-channel MOS transistor 105 is connected to the drain node of theN-channel MOS transistor 101. The constant current source 151 is a loadof the N-channel MOS transistor 105. A gate node of the P-channel MOStransistor 106 is connected to the drain node of the P-channel MOStransistor 102. The constant current source 161 is a load of theP-channel MOS transistor 106. Thus, the N-channel MOS transistor 105 inthe source follower circuit 5 outputs the differential voltage based onvoltage drops developing across the resistance load 103 connected as aload of the N-channel MOS transistor 101. The P-channel MOS transistor106 in the source follower circuit 5 outputs the differential voltagebased on the voltage drops developing across the resistance load 104connected as a load of the P-channel MOS transistor 102.

In the same manner, the source follower circuit 6 serves as an outputcircuit that outputs an upper voltage of the differential signal, andincludes an N-channel MOS transistor 115, a constant current source 152,a P-channel MOS transistor 116, and a constant current source 162. Agate node of the N-channel MOS transistor 115 is connected to the drainnode of the N-channel MOS transistor 111. The constant current source152 is a load of the N-channel MOS transistor 115. A gate node of theP-channel MOS transistor 116 is connected to the drain node of theP-channel MOS transistor 112. The constant current source 162 is a loadof the P-channel MOS transistor 116. Thus, the N-channel MOS transistor115 in the source follower circuit 6 outputs the differential voltagebased on the voltage drops developing across the resistance load 113connected as a load of the N-channel MOS transistor 111. The P-channelMOS transistor 116 in the source follower circuit 6 outputs thedifferential voltage based on the voltage drops developing across theresistance load 114 connected as a load of the P-channel MOS transistor112.

With respect to the above-mentioned configuration, a description will begiven of the limits of the common-mode operation ranges of the N-channeldifferential amplifier circuit 1 and the P-channel differentialamplifier circuit 2 in detail, with reference to FIG. 3.

Referring to FIG. 3, a reference numeral 201 denotes a voltage (Vdsat)that determines a lower limit of the operation of the constant currentsource 140 for the N-channel differential amplifier circuit 1. Areference numeral 202 denotes a threshold voltage (Vgs) for operatingthe N-channel differential element 11 composed of the two N-channel MOStransistors 101 and 111. Therefore, the common-mode operation range ofthe N-channel differential amplifier circuit 1 is denoted by a resultingvoltage Vcm (the reference numeral 203), which is the result where thevoltage Vdsat (the reference numeral 201) and the threshold voltage Vgs(the reference numeral 202) are subtracted from the power supply voltageVcc. In the same manner, a reference numeral 211 denotes a voltage(Vdsat) that determines a lower limit of the operation of the constantcurrent source 141 for the P-channel differential amplifier circuit 2. Areference numeral 212 denotes a threshold voltage (Vgs) for operatingthe P-channel differential element 12 composed of the two P-channel MOStransistors 102 and 112. Therefore, the common-mode operation range ofthe P-channel differential amplifier circuit 2 is denoted by theresulting voltage Vcm (the reference numeral 213), which is the resultwhere the voltage Vdsat (the reference numeral 211) and the thresholdvoltage Vgs (the reference numeral 212) are subtracted from the powersupply voltage Vcc.

As is obvious from FIGS. 2 and 3, it is possible to retain therail-to-rail common-mode range by connecting the respective differentialamplifier circuits (1, 2) in parallel.

Next, as shown in FIG. 2, the topology having the differential amplifiercircuit of the N-channel element connected in parallel with that of theP-channel element has been improved, and the output circuit in thedifferential circuit 200 is designed as the complimentary sourcefollower circuit. A description will be given of the differentialcircuit 200 in detail, with reference to FIG. 4.

As shown in FIG. 4, the differential circuit 200 includes the N-channeldifferential amplifier circuit 1, the P-channel differential amplifiercircuit 2, and the two complementary source follower circuits 15 and 16.

In this configuration, the N-channel differential amplifier circuit 1and the P-channel differential amplifier circuit 2 have the sameconfigurations as shown in FIG. 2.

The complimentary source follower circuit 15 serves as an output circuitthat outputs a lower voltage of the differential signal, and includesthe N-channel MOS transistor 105 and the P-channel MOS transistor 106.The gate node of the N-channel MOS transistor 105 is connected to thedrain node of the N-channel MOS transistor 101. The gate node of theP-channel MOS transistor 106 is connected to the drain node of theP-channel MOS transistor 102. Thus, the N-channel MOS transistor 105 inthe complimentary source follower circuit 15 outputs the differentialvoltage based on the voltage drops developing across the resistance load103 connected as a load of the N-channel MOS transistor 101. TheP-channel MOS transistor 106 in the source follower circuit 15 outputsthe differential voltage based on the voltage drops developing acrossthe resistance load 104 connected as a load of the P-channel MOStransistor 102.

In the same manner, the complimentary source follower circuit 16 servesas an output circuit that outputs an upper voltage of the differentialsignal, and includes the N-channel MOS transistor 115 and the P-channelMOS transistor 116. The gate node of the N-channel MOS transistor 115 isconnected to the drain node of the N-channel MOS transistor 111. Thegate node of the P-channel MOS transistor 116 is connected to the drainnode of the P-channel MOS transistor 112. In the above-mentionedconfiguration, one of the MOS transistors in the complementary sourcefollower circuits (15, 16) serves as a load of the other MOS transistor.Thus, the N-channel MOS transistor 115 in the source follower circuit 16outputs the differential voltage based on the voltage drops developingacross the resistance load 113 connected as a load of the N-channel MOStransistor 111. The P-channel MOS transistor 116 in the source followercircuit 6 outputs the differential voltage based on the voltage dropsdeveloping across the resistance load 114 connected as a load of theP-channel MOS transistor 112.

A description will be given of the operation of the differential circuit200 having the above-mentioned configuration, with reference to FIG. 5.The N-channel MOS transistors 111 and 115, the P-channel MOS transistors112 and 116, the load resistances 113 and 114, and interconnections thatconnect the transistors and the resistances in FIG. 4 are omitted. Inother words, a component (the complementary source follower 16) thatoutputs the upper voltage in the differential signal is omitted.

FIG. 5A is a view describing an operating condition in which the boththe differential amplifier of the N-channel element and that of theP-channel element are operating by the common-mode voltage in the inputcircuit. That is, in the diagram shown in FIG. 5A, the N-channel MOStransistor 101 in the N-channel differential element 11 and theP-channel MOS transistor 102 in the P-channel differential element 12are electrically conducted (on). Therefore, as shown in FIG. 5A, thevoltage output from the N-channel MOS transistor 101 and that outputfrom the P-channel MOS transistor 102 are complimentarily modulated andare applied to nodes 120 and 121 respectively connected to the gate nodeof the N-channel MOS transistor 105 and the gate node of the P-channelMOS transistor 106 in the complimentary source follower circuit 15.Thus, a differential voltage OUTp, which is an output, can be keptconstant.

On the other hand, referring to FIG. 5B, the common-mode voltage in theinput circuit is increased, and the increased voltage exceeds theoperation range of the differential amplifier circuit of the P-channelelement, namely, the P-channel differential amplifier circuit 2. FIG. 5Bis a view describing that only the N-channel differential amplifiercircuit 1, which is the differential amplifier circuit of the N-channelelement, is operating. That is, as shown in FIG. 5B, the N-channel MOStransistor 101 in the N-channel differential element 11 is electricallyconductive (on), and the P-channel MOS transistor 102 of the P-channeldifferential element 12 is not electrically conductive (off). In thismanner, the node 121 turns off the P-channel MOS transistor 102completely, and a current does not flow through the resistance load 104of the P-channel differential element 12, whereas the nodes 120 and 121are respectively connected to the gate nodes of the N-channel MOStransistor 105 and the P-channel MOS transistor 106 shown in FIG. 5B,both of which are included in the complementary source follower circuit15. This results in that the gate node of the P-channel MOS transistor106 in the complementary source follower circuit 15 is constantly biasedto ground potential. Thus, the P-channel MOS transistor 106 in FIG. 5Bonly operates as a load, and the differential circuit 200 operates likean equivalent circuit in which the P-channel MOS transistor 106 isconnected as a load.

In the same manner, if the common-mode voltage in the input circuitdrops, the dropped voltage gets out of the operation range of thedifferential amplifier circuit of the N-channel element, and only thedifferential amplifier circuit in the P-channel element operates. Thatis to say, in the diagrams shown in FIGS. 5A and 5B, the P-channel MOStransistor 102 in the P-channel differential element 12 is electricallyconductive (on), and the N-channel MOS transistor 101 in the N-channeldifferential element 11 is not electrically conducted (off). The node120 turns off the N-channel MOS transistor 101 completely, and a currentdoes not flow through the resistance load 103 in the N-channeldifferential element 11, whereas the nodes 120 and 121 are respectivelyconnected to the gate nodes of the N-channel MOS transistor 105 and theP-channel MOS transistor 106, both of which are included in thecomplementary source follower circuit 15. This results in that the gatenode of the N-channel MOS transistor 105 in the complementary sourcefollower circuit 15 is constantly biased to ground potential. Thus, theN-channel MOS transistor 105 only operates as a load, and the P-channelMOS transistor 106 operates as just a source follower circuit other thanthe complementary source follower circuit to which a load of theN-channel MOS transistor 105 is connected.

FIG. 6 is a graph showing simulation results of the differential circuit200. In this simulation, the common-mode level has been swept from 0 to2.5 V. As is obvious from the graph in FIG. 6, it is found that thedifferential circuit 300 has fluctuating (changing) common-modepotentials of the output voltage in the complementary source followercircuit serving as the output circuit. This is because one of the twoMOS transistors is biased to ground, the two MOS transistors beingrespectively included in the complementary source follower circuits 15and 16 provided as the output circuits, and the two MOS transistorsoperate in different operating modes, as described above. In addition,FIG. 6 shows that the amplitude (hereinafter referred to as gain) of thedifferential output is smaller, when the common-mode level voltage isclose to 0 or 2.5 V.

In this manner, the complementary source follower circuits in the outputcircuit have different operating modes depending on the common modes inthe input circuit. Therefore, it is difficult to stabilize thecommon-mode potential of the output voltage in the complementary sourcefollower circuit serving as the output circuit. Further, there is aproblem in that the gain becomes smaller when the common-mode level iscloser to 0 V or 2.5 V.

Then, the inventors have devised an equivalent circuit that isconfigured to prevent the complementary source follower circuits 15 and16 of the output circuits from operating in common-modes different fromthat of the input circuit. FIG. 7 is a circuit diagram of thedifferential circuit 300 that is designed according to theaforementioned topology. The component (the complementary sourcefollower circuit 16) for outputting the upper voltage in thedifferential signal will be omitted in a description with the use ofFIG. 7 for simplification, and a description will be given of only acase where the common-mode voltage in the input circuit rises.

The above-mentioned fluctuations in the common-mode potentials in theoutput voltage are generated when the common-mode voltage in the inputcircuit rises. This is because a current does not flow through theresistance load 104, when the P-channel MOS transistor 102 completelyturns off. Accordingly, the P-channel MOS transistor 106 included in thecomplementary source follower circuit 15 is biased to ground.

In accordance with the present invention, a bypass circuit is added inorder to introduce a constant current to the load resistance 104 in thedifferential circuit of the P-channel element, if the common-modevoltage in the input circuit exceeds the operation range of thedifferential amplifier circuit of the P-channel element. This bypasscircuit operates as a current supply circuit, and in particularly,operates as a bias input circuit so as to input a given bias potentialto the nodes of the complementary source follower circuits 15 and 16. Itis thus possible to realize the equivalent circuit having the sameconfiguration as the circuit in which the constant-current biasedP-channel MOS transistor is connected to the N-channel MOS transistor105 in the complementary source follower circuit 15 of the outputcircuit as a load element. In the same manner, if the common-modevoltage in the input circuit exceeds the operation range of thedifferential amplifier circuit in the N-channel element, there isprovided a circuit in which the bypass circuit serves as a load in orderto introduce the constant current to the load resistance 103 of thedifferential amplifier circuit in the N-channel element. This bypasscircuit serves as the current supply circuit. Even in the aforementionedcase, it is thus possible to realize the equivalent circuit having thesame configuration as the circuit in which the constant-current biasedN-channel MOS transistor 105 is connected to the P-channel MOStransistor 106 in the complementary source follower circuit 15 of theoutput circuit as a load element.

The above-mentioned current supply circuit pass the current through thenode connected to the load of the differential amplifier circuit (theload resistance 104 and the P-channel MOS transistor 106) from theconstant current source 141 connected to the common node of thedifferential amplifier circuit composed of the P-channel element. Thiscan make it possible to compose the bypass circuit (the current supplycircuit) by connecting the P-channel MOS transistor 502, which is biasedby a bias potential VBp as shown in FIG. 7, to between the respectivenodes.

An Embodiment

Next, a description will be given in detail of an illustrativeembodiment of a differential circuit 400 that is designed according tothe equivalent circuit as shown in FIG. 7. More specifically, thedifferential circuit 400 is designed by adding a topology having acombination of the complementary source follower circuits as the outputcircuits and further adding another topology having the bypass circuitsarranged between the common-modes of the differential amplifier circuitsand the gate node inputs of the complementary source follower circuits,to yet another topology of compensating for the limits of thecommon-mode operation ranges by connecting the differential amplifiercircuit of the N-channel element in parallel with the differentialamplifier circuit of the P-channel element. This bypass circuit operatesas the current supply circuits that supply a given current to the load,when the differential amplifier circuit is not operating.

FIG. 8 is a block diagram of the differential circuit 400. As shown inFIG. 8, the differential circuit 400 includes the N-channel differentialamplifier circuit 1, the P-channel differential amplifier circuit 2, thetwo complementary source follower circuits 15 and 16, a first bypasscircuit 51, and a second bypass circuit 52. The first bypass circuit 51bypasses the N-channel differential element 11. The second bypasscircuit 52 bypasses the P-channel differential element 12. The firstbypass circuit 51 and the second bypass circuit 52 respectively operateas the current supply circuits that supply given currents to thecorresponding loads, when the corresponding differential amplifiercircuits are off.

FIG. 9 shows a circuit diagram of the differential circuit 400 indetail. As is obvious from FIG. 9, the N-channel differential amplifiercircuit 1 includes the N-channel differential element 11, the resistanceloads 103 and 113, and the constant current source 140. The N-channeldifferential element 11 is comprised of a pair of N-channel elements.The P-channel differential amplifier circuit 2 includes the P-channeldifferential element 12, the resistance loads 104 and 114, and theconstant current source 141. The P-channel differential element 12 iscomprised of a pair of P-channel elements. Nodes 130 and 131, among theoutput nodes of the two differential amplifier circuits, are connectedthe complementary source follower circuit 15 composed of the N-channelMOS transistor 105 and the P-channel MOS transistor 106. Nodes 120 and121, among the output nodes of the two differential amplifier circuits,are connected the complementary source follower circuit 16 composed ofthe N-channel MOS transistor 115 and the P-channel MOS transistor 116.

The first bypass circuit 51 includes two N-channel MOS transistors 501and 511 having gate nodes to which a bias potential VBn is applied. Thefirst bypass circuit 51 bypasses the N-channel MOS transistors 101 and111 respectively, and connects the constant current source 140 to thenodes 130 and 120. In the same manner, the second bypass circuit 52includes two P-channel MOS transistors 502 and 512 having gate nodes towhich a bias potential VBp is applied. The second bypass circuit 52bypasses the P-channel MOS transistors 102 and 112 respectively, andconnects the constant current source 141 to the nodes 131 and 121. Inthis manner, it is possible to prevent the N-channel and P-channel MOStransistors 105, 115, 106, and 116 from being biased to ground byrespectively biasing the N-channel and P-channel MOS transistors 501,511, 502, and 512 with constant voltages. As described above, theN-channel and the P-channel MOS transistors 105, 115, 106, and 116compose the complementary source follower circuits 15 and 16respectively, and the N-channel and the P-channel MOS transistors 501,511, 502, and 512 compose the first and second bypass circuits 51 and 52respectively. Other configurations are same as those in FIG. 4, and adescription thereof is omitted here.

FIG. 10 shows simulation results of thus configured differential circuit400. Also in this simulation, the common-mode level has been swept from0 to 2.5 V in order to compare the simulation results shown in FIG. 6,and VBp is set at 1.5 V and VBn is set at 1.0 V. FIG. 10 exhibits thatthe changes (fluctuations) in the common-mode potential have beeneliminated, and the differential circuit 400 has a constant outputvoltage in the complementary source follower circuit serving as theoutput circuit.

The problem of the common-mode potential in the output is solved bydesigning with the above-mentioned topologies. However, another problemof fluctuating gain has not been solved yet. This is exhibited from thesimulation results shown in FIG. 10. Then, the inventors of the presentinvention have founded that a tail current is bypassed by adjusting thebias potentials applied to the gate nodes of the first and second bypasscircuits 51 and 52 so as to solve the problem of the gain.

That is, the problem of the gain can be solved by determining the valuesof the bias potentials VBp and VBn so as to bypass the tail current,while both of the N-channel differential amplifier circuit 1 and theP-channel differential amplifier circuit 2 are operating.

The values of the bias potentials VBp and VBn are independent of aninput signal INp of the N-channel differential amplifier circuit 1 andan input signal INn of the P-channel differential amplifier circuit 2,and are arbitrary constant voltages.

For a simple validation, FIG. 11A shows simulation results of a casewhere the biases are respectively deeper by 0.5 V, by setting VBp andVBn to Vcc/2. FIG. 11B is an enlarged view of the simulation resultsshown in FIG. 10 for comparison. Referring to FIGS. 10A and 10B, thegain has been stabilized by adjusting the bias potentials VBp and VBn,as described.

The differential circuit of the conventional technique 1 shown in FIG. 1has an object of preventing the non-linear operation of the differentialoutput and realizing the stabilization of the circuit. This object isachieved by preventing the operation points of the active loads 810,812, 822, and 824 composed of the P-channel/N-channel MOS transistorsfrom shifting from the linear region into the saturate region, so as tooperate in the linear region at any time. Therefore, the object of thepresent invention cannot be solved by the conventional technique 1. Thedifferential circuit of the conventional technique 1 has the object ofpreventing the non-linear operation in the differential output forstabilization. However, the object of the present invention is tostabilize the common-mode potentials of the output voltages from thecomplementary source follower circuits of the output circuits, becausethe common-mode potentials of the output voltages in the output circuitsvary depending on the different operation mode of the complementarysource follower circuits of the output circuits, which is dependent onthe common-modes of the input circuits. In addition, the feature of thepresent invention is to arrange the first and the second bypass circuits(the current supply circuits) respectively arranged between a constantcurrent source for the N-channel differential element and the outputnode of the differential amplifier circuit and between another constantcurrent source for the P-channel differential element and the outputnode of the differential amplifier circuit. This feature is notdisclosed in the conventional technique 1. Thus, those skilled in theart cannot easily achieve the object of the present invention byapplying the conventional technique 1.

The differential circuit 400 to be designed according to thus configuredequivalent circuit is incorporated into a receiving device 1000, inparticular, a LVDS (Low Voltage Differential Signaling) receiver 1000 asthe differential circuit. In this configuration, the differentialcircuit 400 is provided in the input circuits for the LVDS signals inLVSD input interfaces 1001 and 1002. Here, in this case, a terminatingresistance of the LVDS signal is set at 100 Ω. Also, in theabove-mentioned configuration, the differential circuit 400 is formed ona highly integrated single chip. The receiving device is thus realizedby including the differential circuit having the buffer circuit, whichoutputs the differential output having a constant common-mode potentialwithout a feed back structure and is suitable for driving the loadinside the chip.

Another Embodiment

Although a few preferred embodiments of the present invention have beenshown and described, it would be appreciated by those skilled in the artthat changes may be made in these embodiments without departing from theprinciples and spirit of the invention, the scope of which is defined inthe claims and their equivalents.

As described, the differential circuit and the receiving device havingthe same are thus realized by including the buffer circuit that outputsthe differential output having a constant common-mode potential withouta structure of feed back and is suitable for driving the load inside thechip.

In other words, it is thus possible to eliminate the modulation of theoutput common-mode potential generated by the input common-mode voltage,which is a problem when the rail-to-rail differential amplifier circuitis used for receiving the serial digital transmission signalparticularly in the differential circuit of the serial digitaltransmission signal. It is possible to realize the rail-to-raildifferential circuit including a combination of the buffer circuits,each of which outputs the differential output having a constantcommon-mode potential, and is suitable for driving the load inside thechip.

1. A differential circuit including a differential amplifier circuithaving a differential element provided in a signal input circuit, aconstant current source connected to the differential element, and loadsrespectively connected to the differential element; and a sourcefollower circuit that outputs a differential voltage based on voltagedrops developing across the loads, comprising a current supply circuitthat supplies a given current to the loads connected in series with thedifferential element when the differential element is off and that hasan end connected to a connection node between said loads and saiddifferential element and that has another end connected to a connectionnode between said differential element and said constant current source.2. A differential circuit including a first differential amplifiercircuit having a first differential element provided in a signal inputcircuit, a first constant current source connected to the firstdifferential element, and a first and a second loads respectivelyconnected to the first differential element; a second differentialamplifier circuit having a second differential element provided in thesignal input circuit, a second constant current source connected to thesecond differential element, and a third and a fourth loads respectivelyconnected to the second differential element; a first source followercircuit that outputs a first differential voltage based on voltage dropsdeveloping across the first and second loads; and a second sourcefollower circuit that outputs a second differential voltage based on thevoltage drops developing across the third and fourth loads, comprising afirst current supply circuit that supplies a given current to the firstand second loads when the first differential element is off, said firstcurrent supply circuit having a first current supply circuit end andanother first current supply circuit end, said first current supplycircuit end being connected to a first connection node between saidfirst loads and said second loads and said first differential element,said other first current supply, circuit end being connected to a secondconnection node between said first differential element and said firstconstant current source; and a second current supply circuit thatsupplies the given current to the third and fourth loads when the seconddifferential element is off, said second current supply circuit having asecond current supply circuit end and another second current supplycircuit end, said second current supply circuit end being connected to athird connection node between said third loads and said fourth loads andsaid second differential element, said other second current supplycircuit end being connected to a fourth connection node between saidsecond differential element and said second constant current source. 3.The differential circuit as claimed in claim 2, wherein said firstsource follower circuit includes a first source follower circuitN-channel MOS transistor having a first source follower circuitN-channel MOS transistor end connected to a first power supply (Vcc),another first source follower circuit N-channel MOS transistor endconnected to a first output terminal, and a first source followercircuit N-channel MOS transistor gate connected to the first load, and afirst source follower circuit P-channel MOS transistor having a firstsource follower circuit P-channel MOS transistor end connected to asecond power supply (GND), another first source follower circuitP-channel MOS transistor end connected to the first output terminal, anda first source follower circuit P-channel MOS transistor gate connectedto the second load; and said second source follower circuit includes asecond source follower circuit N-channel MOS transistor having a secondsource follower circuit N-channel MOS transistor end connected to thefirst power supply (Vcc), another second source follower circuitN-channel MOS transistor end connected to a second output terminal, anda second source follower circuit N-channel MOS transistor gate connectedto the third load, and a second source follower circuit P-channel MOStransistor having a second source follower circuit P-channel MOStransistor end connected to the second power supply (GND), anothersecond source follower circuit P-channel MOS transistor end connected tothe second output terminal, and a second source follower circuitP-channel MOS transistor gate connected to the fourth load.
 4. Thedifferential circuit as claimed in claim 2, wherein: the firstdifferential element includes two N-channel MOS transistors having afirst differential, element N-channel MOS transistor ends connected tothe first connection node, another first differential element N-channelMOS transistor end connected to the second connection node and saidfirst differential element having first differential element N-channelMOS transistor gates, said first differential element N-channel MOStransistor gates being connected to each other; the second differentialelement includes two P-channel MOS transistors having a seconddifferential element P-channel MOS transistor ends connected to thethird connection node, another second differential element P-channel MOStransistor end connected to the fourth connection node and said seconddifferential element having second differential element P-channel MOStransistor gates, said second differential element P-channel MOStransistor gates being connected to each other; and bias voltages arerespectively applied to said first differential element N-channel MOStransistor gates and said second differential element P-channel MOStransistor gates so that tail currents flow between said firstdifferential element N-channel MOS transistor ends and seconddifferential element P-channel MOS transistor ends to said other firstdifferential element N-channel MOS transistor end and said other seconddifferential element P-channel MOS transistor end in a state which boththe first and second differential circuits operate.